Title

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ALU, LACG, Clock gating, dynamic power

Authors

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V. Prasanth1, M. Sri Manikyamba2

Keywords

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AND-OR Inverter (AOI), Carry Select Adder (CSLA), Carry Skip Adder (CSKA), Critical Path delay, OR-AND Inverter (OAI), Ripple Carry Adder (RCA), Power consumption

Issue Date

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December – 2015

Abstract

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Any type of digital architecture is modified by using the VLSI technology. In digital systems, clock gating is the best method to reduce consumption of power. As power consumption plays an important role in any integrated circuit. This methodology is mainly used in all type of real world applications and this technology is to enhance the internal architecture level. There are 3 gating methods. The most popularly known gating method is synthesis based. Unfortunately, the Synthetic based gating method leaves the majority of the clock pulses driving the flip flops are terminated. A data driven method halts most of the clock pulses and produces higher power savings, but its application is complex and dependent. The Auto-Gated Flip Flops (AGFF) is the third method which yields moderately lower power saving. This paper introduces a novel Look-Ahead Clock Gating (LACG) method which is the combination of all the three gating methods. It calculates the clock enabling signals of every flip flops one cycle from this time, which it depends on the FFs cycle data at present. In a CPU, the most commonly edited modules is the ALU. During most instruction executions, it is employed. Therefore, a major concern in the ALU is the consumption of power. This paper motivates to reduce the ALU architecture for many digital applications and to improve the internal process in ALU architecture with look ahead clock gating approach. Reduction of delay and power for the data path PE unit in 32 bit ALU architecture.  

Page(s)

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19-24

ISSN

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2347- 4734

Source

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Vol. 2, No.6, December 2015

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