Front Inner Page - Volume 4 No.1 February 2017

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  • Title

    :

    Optimization of Region and Power with Routability Constrained Flip Flop Joining Process

    Authors

    :

    A. Mohamed Noor1, V. Abu Hanifa2

    Keywords

    :

    Clock power, Flip-Flop, Placement, Routability.

    Issue Date

    :

    February 2017

    Abstract

    :

    The main factor considered during designing the in low power and high performance was the power consumption. It plays an important role in the above mentioned region. The concept of multi-bit flip–flop assembled structure has been implemented in the 8-bit shift register circuit and shown the benefits of decreasing the total flip flop region and clock power in a design which was synchronous. At the post placement stage the consequences of implementing multi-bit flip-flops for the purpose of reducing the power consumption of the clock network is attempted. Considering a set of one bit flip–flops with the output and input the capacity constraint, timing constraints and the region constraint in a placement plane, an efficient routability-constrained approach is proposed to obtain multi-bit flip–flops for clock power minimization. Multi-bit flip–flop assembled structure is very successful and productive method in lower-power designs.

    Page(s)

    :

    1-6

    ISSN

    :

    2347- 4734

    Source

    :

    Vol. 4, No.1, February 2017

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